A. Field of the Invention
The present invention relates to a MOSFET semiconductor device having a semiconductor element and a dynamic clamp circuit integrated thereinto, and a control electrode for controlling a current between a pair of major electrodes of the device.
B. Description of the Prior Art
A dynamic clamp circuit is used in a circuit coupled with a inductive load (e.g., a solenoid), to absorb a surge voltage generated by the energy in the inductive load when the current is abruptly shut off. FIG. 1 is a circuit diagram showing such a dynamic clamp circuit, as described in M. Glogolia and M. Jihanyi, Conference Record, IEEE Industrial Application Society Annual Meeting, pp. 429 to 433 (1986).
In FIG. 1, when a power MOSFET Q.sub.0 20 is turned off, a gate terminal G is set at the same potential as a source terminal S. The surge voltage generated in the inductive load (not shown) is applied to a terminal D connected to the drain of MOSFET Q.sub.0 20. A pair of Zener diodes Z.sub.1 21 and Z.sub.2 22 are connected back-to-back between terminal D and a gate resistor R.sub.G. Gate resistor R.sub.G is connected between gate terminal G and the gate electrode of MOSFET Q.sub.0 20.
In this circuit configuration, if the Zener voltage V.sub.Z1 (of Zener diode Z.sub.1 21) is slightly lower than the breakdown voltage of MOSFET Q.sub.0 20, when the potential at drain terminal D reaches the potential V.sub.Z1, Zener diode Z.sub.1 21 breaks down to allow the current to flow through a route of from D to Z.sub.1 to Z.sub.2 to R.sub.G to G. As a result, MOSFET Q.sub.0 20 is turned on, and the urge voltage is absorbed.
When gate electrode G is at a positive potential, the current flows through a route of from G to R.sub.G to Z.sub.1 21 to D (in the absence of Zener diode Z.sub.2 22, and the potential at the gate electrode will not increase. To avoid this, Zener diode Z.sub.2 22 is provided. The circuit will operate similarly if MOSFET Q.sub.0 20 is replaced by a power semiconductor device (e.g., an IGBT or a bipolar transistor) operating under the control of the current flowing to the gate electrode or the base electrode.
FIG. 2 is a cross-sectional view of a dynamic clamp circuit portion of FIG. 1 integrated into a semiconductor chip. The semiconductor chip contains a power vertical MOSFET. In FIG. 2, the semiconductor chip includes a Zener diode group Z.sub.1 which comprises a plurality of Zener diodes Z.sub.1-1 through Z.sub.1-n, and a Zener diode Z.sub.2. Each Zener diode consists of a p.sup.+ anode layer 3, which is formed simultaneously with the p-well (not shown) of the MOSFET (not shown), and an n.sup.+ cathode layer 4 in the surface region of p.sup.+ anode layer 3, which is formed simultaneously with the n.sup.+ source layer (not shown) of the MOSFET. p.sup.+ anode layer 3 and n.sup.+ cathode layer 4 are formed in the surface region of an n.sup.- epitaxial layer 1, to serve as a drift layer on an n.sup.+ substrate 2. n.sup.+ substrate 2 is in contact with a drain electrode 12 of the MOSFET.
n.sup.+ cathode layer 4 of Zener diode Z.sub.2 is connected to the gate electrode (not shown) of the MOSFET via a wire 61. Wire 61 contacts cathode layer 4 through an opening in an interlayer insulating film 52 which covers a field oxide film 51. p.sup.+ anode layer 3 of Zener diode Z.sub.2 is connected to p.sup.+ anode layer 3 of Zener diode Z.sub.1-1, via a wire 62. Each pair of adjacent Zener diodes Z.sub.1-1 and Z.sub.1-n in Zener diode group Z.sub.1, n.sup.+ cathode layer 4 and p.sup.+ anode layer 3 are interconnected via a wire 63.
In FIG. 2, the first Zener diode Z.sub.1-1 and the last Zener diode Z.sub.1-n in order of sequence in Zener diode group Z.sub.1, are shown. Other Zener diodes between these two are not shown for simplicity. n.sup.+ cathode layer 4 of the last Zener diode Z.sub.1-n at one end of Zener diode group Z.sub.1 is connected to an n.sup.+ contact layer 41 via wire 64, and also connected to drain electrode 12 through n.sup.- drift layer 1 and n.sup.+ substrate 2.
The above structure of FIG. 2 having the conventional dynamic clamp circuit integrated into the semiconductor chip containing a vertical MOSFET has a problem in that the breakdown voltage of the chip decreases with respect to that of the MOSFET because of formation of a parasitic bipolar transistor in the chip: the emitter of the parasitic transistor constituted by n.sup.+ cathode layer 4 of Zener diode Z.sub.2 ; the base by a p.sup.+ anode layer; and the collector by n.sup.- drift layer 1 and n.sup.+ substrate 2.
In the structure of FIG. 2, when the MOSFET is turned off, the gate and source terminals of the MOSFET are placed at an equal ground potential; n.sup.+ cathode layer 4 is also grounded; and n.sup.+ substrate 2 in contact with drain electrode 12 is set at a power source potential. Under this condition, the breakdown voltage of the chip is equal to the collector-emitter breakdown voltage V.sub.CEO. The breakdown voltage of the vertical MOSFET is substantially equal to the breakdown voltage between n.sup.- layer 1 and the p.sup.+ -well, which is formed simultaneously with anode layers 3 of Zener diodes Z.sub.1 and Z.sub.2 (i.e., the voltage V.sub.CBO of the parasitic transistor). The relationship between the breakdown voltages V.sub.CEO and V.sub.CBO is generally given EQU V.sub.CEO .perspectiveto.0.5 to 0.7 X V.sub.CBO.
In other words, the breakdown voltage of the chip is determined by V.sub.CEO and approximately equal to 0.5 to 0.7 times the breakdown voltage of the vertical MOSFET. Therefore, when the breakdown voltage of the vertical MOSFET is 130 V, for example, the chip breakdown voltage is 80 V.